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SV51004
2013.05.06
Input Register Bank
Figure 3-2: Variable Precision DSP Block Architecture in 27 x 27 Mode for Stratix V Devices
CLK[2..0]
3-7
scanin [26..0]
ENA[2..0]
chainin[63..0]
ACLR[1..0]
ACCUMULATE
LOADCONST
NEGATE
Constant
Pre-Adder
Multiplier
datab_0[26..0]
dataa_0[26..0]
datac_0[24..0]
27
27
25
+/-
x
+/-
+
COEFSELA[2..0]
Internal
Coefficient
Chainout adder/
accumulator
64
Result[65..0]
scanout[26..0]
chainout[63..0]
Input Register Bank
The input register bank consists of data, dynamic control signals, and two sets of delay registers.
All the registers in the DSP blocks are positive-edge triggered and cleared on power up. Each multiplier
operand can feed an input register or a multiplier directly, bypassing the input registers.
The following variable precision DSP block signals control the input registers within the variable precision
DSP block:
? CLK[2..0]
? ENA[2..0]
? ACLR[0]
In 18 x 18 mode, you can use the delay registers to balance the latency requirements when you use both the
input cascade and chainout features.
One feature of the input register bank is to support a tap delay line; therefore, you can drive the top leg of
the multiplier input (B) from general routing or from the cascade chain, as shown in the following figures.
The Stratix V variable precision DSP block supports 18-bit and 27-bit input cascading.
Variable Precision DSP Blocks in Stratix V Devices
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